看懂用户手册是编写代码的前堤，所以，今天看了一部分的LPC1768用户手册，并根据自己的理解对部分概述进行了中文翻译，整理如下，欢迎大家一起探讨交流。限于个人水平，译文难免有疏漏与错误之处，还望读者批评指正。
1、PLL0控制寄存器
PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency.
PLL0使能。当此位为1时，在一个有效的PLL0反馈信号之后，此位将激活PLL0而且允许它锁定之前请求的频率。
PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz.
PLL0连接。在PLL0被使能而且被锁定之后，设置PLLC0为1，然后随之而来的一个有效的PLL0反馈序列使得PLL0变成CPU、AHB外设总线的时钟源，一般APB外设总线的时钟也由它给出。如果频率为48MHz的话，PLL0输出可能被用做USB子系统的时钟。
2、PLL0配置寄存器
The PLL0CFG register contains PLL0 multiplier and divider values. Changes to the PLL0CFG register do not take effect until a correct PLL feed sequence has been given.
PLL0CFG寄存器包含了PLL0倍频和分频的参数值。直到一个正确的PLL反馈序列被给出，否则PLL0CFG寄存器的更改不会生效。
3、PLL0反馈寄存器
The two writes must be in the correct sequence, and there must be no other register access in the same address space (0x400F C000 to 0x400F FFFF) between them. Because of this, it may be necessary to disable interrupts for the duration of the PLL0 feed operation, if there is a possibility that an interrupt service routine could write to another register in that space. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to the PLL0CON or PLL0CFG register will not become effective.
这两个反馈值的写入必须遵循一个正确的次序，而且在此操作期间，同一地址空间（0X400F C000 - 0X400F FFFF）必须保证没有其他寄存器在进行存取操作。由于这个原因，在PLL0反馈操作期间，失能中断可能是必要的步骤，因为一个中断服务进程很可能在此时对这一地址空间的其他寄存器进行写入。
如果任意一个反馈数值不正确，或者之前提到的条件不满足，任何PLL0CON或PLL0CFG寄存器的更改将不会生效！
4、PLL0设置顺序
1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.
如果PLL0已经连接了，断开其连接并跟随一个反馈序列。
2. Disable PLL0 with one feed sequence.
失能PLL0并跟随一个反馈序列。
3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired.
在没有PLL0的情况下，如果需要，可以通过改变CPU的时钟分频设置来提高运算速率。
4. Write to the Clock Source Selection Control register to change the clock source if needed.
如果需要，对时钟源选择控制寄存进行写操作以改变时钟源。
5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG can only be updated when PLL0 is disabled.
写PLL0CFG寄存器，并且跟随一个反馈序列来使其生效。只有当PLL0没被使能时PLL0CFG寄存器才能被更新。
6. Enable PLL0 with one feed sequence.
使能PLL0与一个反馈序列一起。
7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do this before connecting PLL0.
为PLL0的运算改变CPU的时钟分频设置。在连接PLL0之前去做这件事是至关重要的。
8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register, or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz.
通过监测PLL0STAT寄存器中的PLOCK0位来等待PLL0完成锁定、或者使用PLOCK0中断、或者当PLL0的输入时钟很慢时等待一个固定的时间点。当PLL参考频率（FREF，它是REFCLK的频率，等于经由预分频器中的值分频后的PLL输入频率）小于100KHz或者大于20MHz时，PLOCK0的值也许不是稳定的。在这种情况下，当一个启动时间过后，PLL可能被假定为是稳定的。当FREF大于400KHz时，这个启动时间为500us；当FREF小于400KHz时，这个启动时间为(200/FREF)s.
9. Connect PLL0 with one feed sequence.
连接PLL0并跟随一个反馈序列。
It is very important not to merge any steps above. For example, do not update the PLL0CFG and enable PLL0 simultaneously with the same feed sequence.
有一点很重要：不要合并上文中的任何步骤。例如，不要在同一个反馈序列时更新PLL0CFG并同时使能PLL0。
5、USB时钟配置寄存器
This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in PLL1CON). If PLL1 is connected, its output is automatically used as the USB clock source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB subsystem. If PLL1 is not connected, the USB subsystem will be driven by PLL0 via the USB clock divider.
USBCLKCFG寄存器只有当PLL(PLL1)未连接（通过PLL1CON寄存器的PLLC1位进行选择）时才被使用。如果PLL1被连接，它的输出自动地被用做USB时钟源，而且PLL1必须被配置为给USB子系统提供正确的48MHz的时钟。如果PLL1未连接，USB子系统将经由USB时钟分频器，通过PLL0来对其进行驱动。
The USBCLKCFG register controls the division of the PLL0 output before it is used by the USB subsystem.The PLL0 output must be divided in order to bring the USB clock frequency to 48 MHz with a 50% duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL operating range.
USBCLKCFG寄存器控制PLL0输出的分配，在其被用于USB子系统使用之前。为了供USB使用，PLL0输出必须被分成频率48MHz，占空比50%的时钟信号。一个4位的分频器允许获取到正确的USB时钟在PLL工作范围之内，从48MHz的任意偶数倍。
（版权归属于NXP Semiconductors，本文只限于交流用途）
